As various electronic devices including a personal computer, a digital camera, and a mobile phone progress toward downsizing and higher performance, requirements are rapidly increasing for further downsizing, thinning, and densifying in semiconductor devices. Accordingly, it is desired to develop an insulating material, a stacked semiconductor apparatus, and a method for manufacturing the same that can cope with an increase in surface area of a substrate for the sake of higher productivity, and can be used in high density mounting technologies including a chip size package or a chip scale package (CSP) and a three-dimensional lamination.
Furthermore, along with the development of electronic devices toward downsizing and higher performance, a process for manufacturing semiconductor devices has also developed to meet requirements for high density and high function in semiconductor devices. For example, the semiconductor devices are shifted to fragile one having a fine wiring rule to cope with a narrow pitch and a high speed processing and using a ultra-low dielectric material to cope with a high frequency.
Conventional examples of a method for manufacturing a semiconductor apparatus by connecting an electrode formed on a semiconductor device to an interconnect pattern formed on a substrate include connection between the semiconductor device and the substrate by wire bonding. However, the connection between the semiconductor device and the substrate by wire bonding requires a space for drawing metal wire on the semiconductor device. This makes the apparatus large, resulting in difficulty downsizing. Thus, this method cannot meet requirements for high density mounting. Therefore, wafer bonding for bonding substrates each having a wiring, chip scale package for mounting semiconductor devices on a substrate, and flip-chip mounting are devised as methods for mounting semiconductor devices to realize three-dimensional mounting. In particular, the flip-chip mounting, which uses bumps on electrodes for short wiring connection, is desirable to make use of circuit characteristics of semiconductor devices having a fine wiring rule to cope with a narrow pitch and a high speed processing and using a ultra-low dielectric material to cope with a high frequency. Moreover, bump formation and mounting are required to be performed under a low load to cope with the fragility of the semiconductor devices.
Under such circumstances, a method for forming bumps, for use in flip-chip mounting, on electrodes of semiconductor devices has been proposed. In this technique, a photosensitive resin layer body is pressure-bonded to an electrode-forming surface of a base such as a semiconductor substrate or a wafer under heating, the photosensitive resin layer body is subjected to exposure and development to form openings on electrodes, and the electrodes exposed to the openings are plated to form bumps (See PATENT LITERATURE 1, for example).
The conventional method for manufacturing the bump-attached semiconductor device will now be described with reference to FIGS. 9(a) and 9(b).
Manufacturing the bump-attached semiconductor device begins with, as shown in FIG. 9(a), applying a photosensitive polyimide resin 2101 on an electrode-forming surface of a semiconductor device or a substrate 2102. After drying the resin, part of the photosensitive polyimide resin 2101 on electrode pads 2110 is removed by mask exposure and development to form openings. The photosensitive polyimide resin 2101 is then thermally cured to be used as a protective film, and bumps 2114 are formed by plating on the electrode pads 2110 exposed to the openings, as shown in FIG. 9(b), whereby the bump-attached semiconductor device 2120 is obtained. The plating may be performed, for example, after forming a passivation film such as a Ti film on aluminum electrode pads 2110 of the semiconductor device or the substrate 2102, plating the film with Cr or Ni and further Au to form plating bumps 2114 with a total thickness of about 5 to 30 μm.
In the above conventional example, when the bumps are formed with a narrow pitch to meet the recent requirement, via holes formed in the on-electrode portion of the protective film have small diameter to achieve the narrow pitch. However, such openings, so-called via holes, have high aspect ratio so that a plating solution for forming the bumps is difficult to enter and renew therein. This reduces plating rate and easily causes variation of thickness of the plating layer.
Furthermore, since the plating bump is a rigid metal bump, this bump cannot achieve a sufficient following deformation under a low load stress for avoiding breakage of the fragile semiconductor device. To deform the bump of the semiconductor device in accordance with warpage and waviness of a circuit board and achieve electrical connection in flip-chip mounting, a high load is necessary in flip-chip mounting. Unfortunately, the high load easily breaks the recent fragile semiconductor devices using a ultra-low dielectric material and damages active elements under their electrodes.
To solve this problem, PATENT LITERATURE 2 proposes a bump-attached semiconductor device including a protective film formed on an electrode-forming surface and a bump electrically connected to an electrode and protruding from the protective film, in which the protective film is provided with a via hole connecting to the electrode, the via hole contains a via post composed of a conductive resin and electrically connected to the electrode, and the via post has the bump protruding from the surface of the protective film. This bump-attached semiconductor device includes the via post composed of a conductive resin excellent in stress absorption within the via hole, thus enabling deformation in accordance with warpage and waviness of a circuit board even under a low load.
Besides, a semiconductor-device-mounting substrate in which a semiconductor device having a bump is connected to a substrate by flip-chip mounting as is has a remarkably low reliability of wet resistance since an electrode portion of the semiconductor is exposed to the air. In addition, there is another problem that a stress applied to the electrode junction makes the connection detached.
To improve reliability of the junction after connecting the bump and the circuit board, the following method is employed: a space between the semiconductor device and the circuit board is filled with a liquid resin, called an underfilling material, followed by curing to fix the semiconductor device and the circuit board.
However, a semiconductor device especially used in flip-chip mounting usually has many electrodes. These electrodes are disposed around the semiconductor device depending on a circuit design of the semiconductor device. At filling with the underfilling material, the liquid resin is poured into a space between the electrodes of the semiconductor device through gravity and a capillary phenomenon. However, when the distance between the semiconductor device and the circuit board is narrow about 10 μm to 500 μm, the liquid resin cannot reach the center of the semiconductor device, which leads to an unfilled portion and destabilizes operation of the semiconductor device. Moreover, filling with the underfilling material through a gravity and a capillary phenomenon takes a long time. Furthermore, electrical connection between the electrode of the semiconductor device and the circuit board easily causes a short circuit of a conductive resin and solder due to a narrow electrode interval.
To solve these problems, PATENT LITERATURE 3 proposes fixing a semiconductor device with a thermoplastic insulating adhesive film having a glass transition temperature lower than a temperature at which a bump of the semiconductor device is connected when the bump electrode of the semiconductor device is directly connected to a circuit board. In PATENT LITERATURE 3, the bump electrode is put into the insulating adhesive film that has been softened by heating so as to pierce the insulating adhesive film, whereby the circuit board and the bump electrode of the semiconductor device are connected. However, this method has a low material selectivity of the insulating adhesive film, and is insufficient in adhesion between the circuit board and the semiconductor device.